Securing Reconfigurable Systems: Real-Time ML-Based Hardware Trojan Detection via Binary FPGA Bitstream Analysis

Authors

• Rye C. Stahle-Smith Mr., University of South Carolina - ColumbiaFollow

Abstract

Reconfigurable computing platforms such as Field-Programmable Gate Arrays (FPGAs) are widely deployed in high-performance embedded systems and AI acceleration workloads. Their post-deployment reconfigurability, however, introduces a critical attack surface: maliciously crafted configuration bitstreams can embed hardware Trojans capable of leaking sensitive data, degrading system reliability, or silently altering computation. This paper presents an AI-based predictive modeling framework for detecting malicious FPGA configurations directly from binary bitstreams, without reliance on source code or netlists. Bitstreams sourced from state-of-the-art (SOTA) Trust-Hub benchmarks were re-engineered for the Xilinx PYNQ-Z1 platform and labeled as benign, malicious, or empty. A 256-dimensional byte-frequency feature vector is extracted from each bitstream, compressed using Truncated Singular Value Decomposition (TSVD), and balanced with SMOTE to address class imbalance prior to supervised classification. Among the evaluated classifiers, a Random Forest model achieves a macro F1-score of 0.97 on held-out test data while remaining feasible for on-device deployment on the PYNQ-Z1, validating the effectiveness of AI-driven bitstream screening in resource-constrained environments.

Recommended Citation

Stahle-Smith, Rye C. Mr. (2026) "Securing Reconfigurable Systems: Real-Time ML-Based Hardware Trojan Detection via Binary FPGA Bitstream Analysis," Caroliniana Undergraduate Research Journal: Vol. 1: Iss. 2, Article 5.
Available at: https://scholarcommons.sc.edu/usc-curj/vol1/iss2/5