Date of Award

5-2017

Document Type

Open Access Thesis

Department

Electrical Engineering

First Advisor

Herbert L. Ginn

Abstract

Power-Hardware-In-the-Loop (PHIL) simulations allow the design and validation of power hardware components in virtual power system schemas with near real-time operation. This technique is increasingly used in the development cycle of many products to reduce design costs and increase design fidelity. The Hardware under Test (HuT) interfaces with a simulation of the user’s choosing through a hardware interface (HI). The digitally simulated system (DSS) runs on the real-time simulator before sending a reference value to the hardware interface to enforce. In this virtual to real interface, closed-loop stability and the simulation accuracy are the two paramount criteria in regards to the operational safety and experimental reliability.

The stability of the PHIL simulation represents the highest challenge in the implementation of this digitally simulated power system. The interface between the HuT and the DSS ideally adds zero distortion and maintains a unity gain. In practice, PHIL methods each have stability and accuracy trade-offs that will be discussed.

Any delay present in the simulation may negatively damp the system into unstable conditions. Careful consideration and compensation of interface delays can alleviate these adverse conditions. By communicating via time-frequency communication and partitioning a Point of Common Coupling (PCC) into the Hardware Interface controller, complex linear and nonlinear circuits may be simulated in a safe, stable and accurate environment.

Analysis and verification of this thesis has been tested using a PHIL testbed at the University of South Carolina. The PHIL testbed is composed of a TI TMS320F28335 digital signal processor, Opal-RT real-time simulator, and Matlab/Simulink.

Rights

© 2017, Sean Borgsteede

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