Elie Kfoury

Date of Award

Summer 2023

Document Type

Open Access Dissertation


Computer Science and Engineering

First Advisor

Jorge Crichigno


The performance of networks today is drastically affected by: 1) switches equipped with large buffers, referred to as “bloated buffers”: due to the lack of programmability and traffic visibility in legacy switches, operators nowadays configure large buffers statically without considering the characteristics or dynamics of flows. Such buffers increase the delays on packets, causing the Quality of Service (QoS) of networked applications (e.g., voice over IP, web browsing) to degrade; 2) switches forwarding packets on a best-effort basis: traffic crossing a switch is heterogeneous in many ways. Mixing such traffic in a single queue without any QoS measures can drastically degrade the performance of certain applications and cause fairness issues among flows; 3) CPU-based packet processors (middleboxes): latency and jitter increase when packets are processed by a general-purpose CPU, especially when the traffic rates are high.

Recently, data plane programmability has attracted significant attention from both the research community and the industry, permitting operators to develop and run customized packet processing functions.

The objective of this dissertation is to leverage Programmable Data Plane (PDP) switches to address the aforementioned performance issues. The contributions are: i) Improving the QoS by dynamically sizing the buffer. Live measurements derived using a passively deployed PDP are used to dynamically modify the buffer size in a closed loop. The selected buffer size minimizes packet loss and queueing delays. ii) Improving the QoS and fairness through traffic classification and separation. A passive PDP executes measurements to classify flows based on their congestion control algorithm, round-trip time, and flow size. After classification, the flows are assigned to dedicated queues, which improves the QoS and fairness. iii) Scaling and optimizing media’s QoS by offloading packet processing from a CPU to a PDP. The media relay functionality, which is implemented on a general-purpose CPU, is offloaded to a PDP, which improves the QoS and the scalability of media sessions. iv) Fostering PDP adoption by proposing a passive deployment architecture. A cost-efficient architecture that uses passive PDPs coupled with optical Traffic Access Points (TAPs) is presented. The PDPs run customized packet processing functions that collect network information with nanosecond resolution. This visibility enables intelligent algorithms residing in the control plane to construct configuration rules and apply them to legacy devices. v) Identifying the challenges and trends of PDPs. Twelve challenges and their associated research directions in the area of PDP are presented.