Date of Award

2017

Document Type

Open Access Dissertation

Department

Electrical Engineering

Sub-Department

College of Engineering and Computing

First Advisor

Electrical Engineering

Abstract

Demand for smaller platform sizes with increasing bandwidth has driven crosstalk problems that prevent bus performance to scale with Moore’s Law. Several approaches to reduce crosstalk such as the use of shields, differential links, and equalizers have been rejected due to higher cost and power required to overcome the signal integrity impediments at Gigahertz data rates. Eigen-mode signaling based on modal decomposition techniques is the most recent method to mitigate crosstalk that can potentially satisfy the demand for higher data rates from modern technology industry.

The goal of this research is to allow maximum dense routing between packages on PCBs and to maximize bus bandwidth per unit volume for small form factors at high data rates. Crosstalk became a significant problem in interconnect designs that limit data rates and routing densities. A modal decomposition technique is an alternative approach to reduce crosstalk where each mode carries a single bit of data. Studies show this concept is capable of mitigating crosstalk with achievable dense routing and higher bandwidth. Nevertheless, the complexity of this method leads to higher cost in terms of power needed and additional circuit implementation that makes it too high to be an alternative method to replace traditional binary signaling. “Crosstalk Harnessed Signaling” (CHS) is another possible technique to reduce the complexity of modal decomposition. This technique was invented to encode data so that each bit is spread across multiple conductors such that crosstalk becomes part of the signal and can be removed during decode. A CHS concept is a possible choice to mitigate crosstalk with higher densely routing, higher bandwidth and less complexity compared to existing Eigen-mode signaling techniques.

In this research, 3D novel routing will be introduced to maximize cross-sectional density by >10X and bandwidth gains of up to 31X for 4 layer matrix at DDR4 4266MT/s by implementing a CHS concept. In this proposal, the research will demonstrate the advantages of 3D CHS routing over 2D CHS routing with simulations that include performance, efficiency, speed, cost and power to maximize bandwidth per unit volume. This research will also consider other geometric configurations that can potentially increase the bandwidth per unit volume by altering trace thickness, 3D layout topologies, material properties and spacing. Cost is always a core factor to drive the acceptance of novel engineering concepts into the market. Thus, Return On Investment (ROI) studies will be part of this research and will include implementation of the CHS concept into small form factor devices, cables and connectors.

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