Date of Award


Document Type

Open Access Thesis


Electrical Engineering

First Advisor

Yinchao Chen


In high-speed, high density PCB bus systems, high frequency signal losses and crosstalk can have great impacts on signal integrity and digital timing, which can distort transmitted signals, worsen eye diagrams, and attenuate signal amplitudes. Also, these impacts make digital signals and their energy smearing over multiple bit positions as known as jitters, and cause the phenomenon of inter-symbol interference (ISI) in digital signal transmissions.

The main objective of this thesis is to analyze and develop efficient topology circuits for compensating bus system high frequency losses by using equalization techniques. The thesis has focused on study of various practical and efficient circuit topologies in order to improve its digital signals at receiver ends. The investigated equalization topologies include a shunt RC, series RL, Maxim's, Agilent's, and proposed equalizer circuits. It is found that with the application of the proposed equalization techniques, the quality of digital signals and eye diagrams is really improved up to the 50 inch lossy channels by using both the post-emphasis and de-emphasis compensation techniques.

Signal Integrity is an important research area in high-speed, high density digital transmission systems, and many factors, such as transmission line loss, circuit discontinuities, and non-linearity of passive and active components can easily distort signal quality to make them becomes unreliable in particular at high frequencies. Equalization is a powerful technique to restore distorted signals, which employs passive component as an equalizer applied to wired transmission channels.

A distorted signal can be resulted from different sources. One of dominant contributions is transmission line contains loss, including both conductor and dielectric losses. For a digital signal, jitter is an important characterization of distorted signals, which describes the signal turbulence in the time domain and time delay makes the signal postponed in a communication system.

This thesis mainly focuses the topology analysis, improvement, and development of passive equalizers, including shunt RC and series RL circuit equalizers. It is found these circuits can be applied to an interconnection solely, or combined with these two circuits as a RLC circuit. With this topology, the eye probe receives higher signal quality and less jitters. The delay and jitter are minimized after the compensation circuit applied. After the optimization, relocate the equalizer circuit before the transmission line and discuss the different influence on the signal.


© 2013, Kuo-Lun Yen