Wireless Networks-on-Chips: Architecture, Wireless Channel, and Devices

Author(s)

David W. Matolak, University of South Carolina - ColumbiaFollow
Avinash Kodi
Savas Kaya
Dominic DiTomaso
Soumyasanta Laha
William Rayess

Document Type

Article

Subject Area(s)

Electrical and Computer Engineering

Abstract

Wireless networks-on-chips (WINoCs) hold substantial promise for enhancing multicore integrated circuit performance, by augmenting conventional wired interconnects. As the number of cores per IC grows, intercore communication requirements will also grow, and WINoCs can be used to both save power and reduce latency. In this article, we briefly describe some of the key challenges with WINoC implementation, and also describe our example design, iWISE, which is a scalable wireless interconnect design. We show that the integration of wireless interconnects with wired interconnects in NoCs can reduce overall network power by 34 percent while achieving a speedup of 2.54 on real applications.

Publication Info

Postprint version. Published in IEEE Wireless Communications, Volume 19, Issue 5, 2012, pages 58-65.

© IEEE Wireless Communications, 2012, IEEE

Matolak, D., Kodi, A., Kaya, S., DiTomaso, D., Laha, S., Rayess, W. (2012). Wireless Networks-on-Chips: Architecture, Wireless Channel, and Devices. IEEE Wireless Communications, 19(5), 58-65.

http://dx.doi.org/10.1109/MWC.2012.6339473

Rights

© IEEE Wireless Communications, 2012, IEEE

Matolak, D., Kodi, A., Kaya, S., DiTomaso, D., Laha, S., Rayess, W. (2012). Wireless Networks-on-Chips: Architecture, Wireless Channel, and Devices. IEEE Wireless Communications, 19(5), 58-65.

http://dx.doi.org/10.1109/MWC.2012.6339473