Document Type
Article
Subject Area(s)
Computer Science and Engineering
Abstract
In this paper, we describe the design for a co-processor for whole-genome phylogenetic reconstruction. Our current design performs a parallelized breakpoint median computation, which is an expensive component of the overall application. When implemented on a field-programmable gate array (FPGA), our hardware breakpoint median achieves a maximum speedup of 1005times over software. When the coprocessor is used to accelerate the entire reconstruction procedure, we achieve a maximum application speedup of 417times. The results in this paper suggest that FPGA-based acceleration is a promising approach for computationally expensive phylogenetic problems, in spite of the fact that the involved algorithms are based on complex, control-dependent combinatorial optimization.
Publication Info
Published in IEEE Transactions on Very Large Scale Integration, Volume 16, Issue 12, 2008, pages 1666-1676.
http://ieeexplore.ieee.org/servlet/opac?punumber=92
© 2008 by the Institute of Electrical and Electronics Engineers (IEEE)
Rights
http://ieeexplore.ieee.org/servlet/opac?punumber=92
© 2008 by the Institute of Electrical and Electronics Engineers (IEEE)