Date of Award

1-1-2013

Document Type

Open Access Dissertation

Department

Electrical Engineering

First Advisor

Enrico Santi

Abstract

Thanks to recent progress in SiC technology, SiC JFETs, MOSFETs and Schottky diodes are now commercially available from several manufactories such as Cree, GeneSiC and Infineon. SiC devices hold the promise of faster switching speed compared to Si devices, which can lead to superior converter performance, because the converter can operate at higher switching frequencies with acceptable switching losses, so that passive filter size is reduced. However, the ultimate achievable switching speed is determined not only by internal semiconductor device physics, but also by circuit parasitic elements. Therefore, in order to accurately predict switching losses and actual switching waveforms, including overshoot and ringing, accurate models are needed not only for the semiconductor devices, but also for the circuit parasitics.

In this dissertation, a new physics-based model accounting for non-uniform current distribution in JFET region for the power SiC DMOSFET is presented. Finite element simulation shows that current saturation for typical device geometry is due to two-dimensional (2-D) carrier distribution effects in JFET region caused by current spreading from the channel to the JFET region. Based on this phenomenon, a new model is proposed that represents the non-uniform current distribution in the JFET region using a non-linear voltage source and a resistance network. Advantages of the proposed model are that a single set of equations describes operation in both the linear and saturation regions, and that it provides a more physical description of MOSFET operation. The model represents an original contribution in the area of physics-based power semiconductor device modeling. This model is validated both statically and under resistive conditions for SiC DMOSFET showing overall good matching with experimental results and finite element simulations.

This dissertation also presents a simple physics-based power Schottky diode model which is comprised of a voltage controlled current source, a temperature dependent drift region resistance and a nonlinear capacitance. A detailed parameter extraction procedure for this model is also discussed in this work. The developed procedure includes the extraction of doping concentration, active area and thickness of drift region, which are needed in the power Schottky diode model. The main advantage is that the developed procedure does not require any knowledge of device fabrication, which is usually not available to circuit designers. The only measurements required for the parameter extraction are a simple static I-V characterization and C-V measurements. Furthermore, the physics-based SiC Schottky diode model is also temperature dependent and is generally applicable to SiC Schottky diodes. This procedure is demonstrated for four different Schottky diodes from two different manufacturers. The parameter extraction procedure represents an original contribution in the area of characterization of power semiconductor devices.

In order to capture the parasitic ringing in the very fast switching transients, a procedure to accurately model circuit parasitics is also presented. A double pulse test-bench was built to characterize the resistive and inductive switching behavior of the SiC devices. The parasitic inductances for resistive and inductive switching of SiC devices in this switching test circuit were modeled and analyzed using a three-dimensional (3-D) inductance extraction program. The gate-to-source switching loop and drain-to-source switching loop parasitic inductances of the PCB layout are extracted and simulated together with previously developed power SiC device models in Pspice. Simulation results show good agreement with experimental results under both resistive and inductive switching conditions.

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