Document Type
Conference Proceeding
Subject Area(s)
Computer Science and Engineering
Abstract
This paper presents a novel reconfigurable data flow processing architecture that promises high performance by explicitly targeting both fine- and course-grained parallelism. This architecture is based on multiple FPGAs organized in a scalable direct network that is substantially more interconnect-efficient than currently used crossbar technology. In addition, we discuss several ancillary issues and propose solutions required to support this architecture and achieve maximal performance for general-purpose applications; these include supporting IP, mapping techniques, and routing policies that enable greater flexibility for architectural evolution and code portability.
Publication Info
Published in Proc. 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'06), 2006, pages 121-130.
http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=4020883
© 2006 by the Institute of Electrical and Electronics Engineers (IEEE)
Rights
http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=4020883
© 2006 by the Institute of Electrical and Electronics Engineers (IEEE)